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4-channel, 200 ksps 12-bit adc with sequencer in 16-lead tssop data sheet ad7923 rev. d document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2002C2013 analog devices, inc. all rights reserved. technical support www.analog.com features fast throughput rate: 200 ksps specified for av dd of 2.7 v to 5.25 v low power 3.6 mw max at 200 ksps with 3 v supply 7.5 mw max at 200 ksps with 5 v supply 4 (single-ended) inputs with sequencer wide input bandwidth 70 db min snr at 50 khz input frequency flexible power/serial clock speed management no pipeline delays high speed serial interface spi ? -/qspi tm -/ microwire tm -/dsp-compatible shutdown mode: 0.5 a max 16-lead tssop package qualified for automotive applications general description the ad7923 is a 12-bit, high speed, low power, 4-channel, suc- cessive approximation (sar) adc. it operates from a single 2.7 v to 5.25 v power supply and features throughput rates up to 200 ksps. it contains a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 8 mhz. the conversion process and data acquisition are controlled by cs and the serial clock, allowing the device to easily interface with microprocessors or dsps. the input signal is sampled on the falling edge of cs ; the conversion is also initiated at this point. the ad7923 uses advanced design techniques to achieve very low power dissipation at maximum throughput rates. at maximum throughput rates, it consumes 1.2 ma maximum with 3 v supplies and 1.5 ma maximum with 5 v supplies. through the configuration of the control register, the analog input range can be selected as 0 v to ref in or 0 v to 2 ref in , with either straight binary or twos complement output coding. the ad7923 features four single-ended analog inputs with a channel sequencer to allow a preprogrammed selection of channels to be converted sequentially. the conversion time for the ad7923 is determined by the serial clock, sclk, frequency, since this is used as the master clock to control the conversion. the conversion time can be as short as 800 ns with a 20 mhz sclk. functional block diagram ? ? ? ? ? ? ? ? ? ? ? ? ? v in 3 t/h i/p mux sequencer control logic 12-bit successive approximation adc gnd sclk dout din cs v drive av dd ad7923 ref in v in 0 03086-001 figure 1. product highlights 1. high throughput with low power consumption. the ad7923 offers up to 200 ksps throughput rates. at the maximum throughput rate with 3 v supplies, the ad7923 dissipates just 3.6 mw of power. 2. four single-ended inputs with a channel sequencer. 3. single-supply operation with v drive function. the v drive function allows the serial interface to connect directly to either 3 v or 5 v processor systems independent of av dd . 4. flexible power/serial clock speed management. the conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. the part also features various shutdown modes to maximize power efficiency at lower throughput rates. current consumption is 0.5 a maximum when in full shutdown. 5. no pipeline delay. the part features a sar adc with accurate control of the sampling instant via a cs input and once off conversion control.
ad7923* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. evaluation kits ? ad7923 evaluation kit documentation application notes ? an-742: frequency domain response of switched- capacitor adcs ? an-931: understanding pulsar adc support circuitry data sheet ? ad7923-dscc: military data sheet ? ad7923-ep: enhanced product data sheet ? ad7923: 4-channel, 200 ksps, 12-bit adc with sequencer in 16-lead tssop data sheet product highlight ? 8- to 18-bit sar adcs ... from the leader in high performance analog technical books ? the data conversion handbook, 2005 reference materials product selection guide ? sar adc & driver quick-match guide technical articles ? ms-1779: nine often overlooked adc specifications ? ms-2210: designing power supplies for high speed adc tutorials ? mt-001: taking the mystery out of the infamous formula, "snr=6.02n + 1.76db", and why you should care ? mt-002: what the nyquist criterion means to your sampled data system design ? mt-031: grounding data converters and solving the mystery of "agnd" and "dgnd" design resources ? ad7923 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7923 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad7923 data sheet rev. d | page 2 of 24 table of contents specifications ..................................................................................... 3 timing specifications ....................................................................... 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function description .............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 10 control register descriptions ...................................................... 12 sequencer operation ................................................................. 13 theory of operation ...................................................................... 14 circuit information .................................................................... 14 converter operation .................................................................. 14 adc transfer fun ction ............................................................. 15 typical connection diagram ................................................... 16 modes of operation ................................................................... 17 pow ering up the ad7923 ......................................................... 18 power vs. throughput rate ....................................................... 19 serial interface ............................................................................ 20 microprocessor interfacing ....................................................... 21 application hints ........................................................................... 23 grounding and layout .............................................................. 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 automotive products ................................................................. 24 revision his tory 6 / 13 rev. c to rev . d deleted evaluating the ad7923 performance section .............. 23 changes to ordering guide .......................................................... 24 5 / 11 rev. b to rev . c changes to features section ............................................................ 1 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 added to automotive products section ...................................... 24 1 2 /08 rev. a to rev. b changes to esd parameter, table 3 ............................................... 6 changes to ordering guide .......................................................... 24 8 /05 rev. 0 to rev. a update format .................................................................... universal change to table 1 ............................................................................. 3 chan ge to table 3 ............................................................................. 6 change to reference section ......................................................... 16 changes to ordering guide .......................................................... 24 11/02 revision 0: initial version
data sheet ad7923 rev. d | page 3 o f 24 specifications av dd = v drive = 2.7 v to 5.25 v, ref in = 2.5 v, f sclk = 20 mhz, t a = t min to t max , un less otherwise noted. table 1 . parameter b version 1 unit test conditions/comments dynamic performance f in = 50 khz sine wave, f sclk = 20 mhz signal -to - (noise + distortion) ( sinad ) 2 70 db min @ 5 v, C 40c to + 85c 69 db min @ 5 v, 85c to 125c, typ 70 db 69 db min @ 3 v typ 70 db , C 40c to + 125c signal -to - noise (snr) 2 70 db min total harmonic distortion (thd) 2 ?77 db max @ 5 v typ , ?84 db ?73 db max @ 3 v typ , ?77 db peak harmonic or spurious noise ?78 db max @ 5 v typ , ?86 db (sfdr) 2 ?76 db max @ 3 v typ , ?80 db intermodulation distortion (imd) 2 f a = 40.1 khz, f b = 41.5 khz second order terms ?90 db typ third order terms ?90 db typ aperture delay 10 ns typ aperture jitter 50 ps typ channel -to - channel isolation ?85 db typ f in = 400 khz full power bandwidth 8.2 mhz typ @ 3 db 1.6 mhz typ @ 0.1 db dc accuracy 2 resolution 12 bits integral nonlinearity 1 lsb max differential nonlinearity ?0. 9/+1.5 lsb max guaranteed no missed codes to 12 bits 0 v to ref in input range straight binary output coding offset error 8 lsb max typ 0.5 lsb offset error match 0.5 lsb max gain error 1.5 lsb max gain error match 0.5 lsb max 0 v to 2 ref in input range ?ref in to +ref in biased about ref in with twos complement output coding positive gain error 1.5 lsb max positive gain error match 0.5 lsb max zero - code error 8 lsb max typ 0.8 lsb zero - code error match 0.5 lsb max negative gain error 1 lsb max negative gain error match 0.5 lsb max analog input input voltage range 0 to ref in v range bit set to 1 0 to 2 ref in v range bit set to 0, av dd = 4.75 v to 5.25 v dc leakage current 1 a max input capacitance 20 p f typ reference input ref in input voltage 2.5 v 1% specified performance dc leakage current 1 a max ref in input impedance 36 k? typ f sample = 200 ksps logic inputs input high voltage, v inh 0.7 v drive v min input low voltage, v inl 0.3 v drive v max input current, i in 1 a max typ 10 na, v in = 0 v or v drive input capacitance, c in 3 10 pf max
ad7923 data sheet rev. d | page 4 of 24 parameter b version 1 unit test conditions/comments logic outputs output high voltage, v oh v drive C 0.2 v min i source = 200 a, av dd = 2.7 v to 5.25 v output low voltage, v ol 0.4 v max i sink = 200 a floating - state leakage current 1 a max floating - state output capacitance 3 10 pf max output coding twos complement coding bit set to 0 straight (natural) binary coding bit set to 1 conversion rate conversion time track - and - hold acquisition time 800 ns max 16 sclk cycles with sclk at 20 mh z 300 ns max sine wave input 300 ns max full - scale step input throughput rate 200 ksps max see serial interface secti on power requirements av dd 2.7/5.25 v min/max v drive 2.7/5.25 v min/max i dd 4 digital i/ps = 0 v or v drive during conversion 2.7 ma max av dd = 4.75 v to 5.25 v, f sclk = 20 mhz 2.0 ma max av dd = 2.7 v to 3.6 v, f sclk = 20 mhz normal mode (static) 600 a typ av dd = 2.7 v to 5.25 v, sclk on or off normal mode (operational) f sample = 20 0 ksps 1.5 ma max av dd = 4.75 v to 5.25 v, f sclk = 20 mhz 1.2 ma max av dd = 2.7 v to 3.6 v, f sclk = 20 mhz using auto s hutdown mode f sample = 200 ksps 900 a typ av dd = 4.75 v to 5.25 v, f sample = 200 ksps 650 a typ av dd = 2.7 v to 3.6 v, f sample = 200 ksps auto shutdown (static) 0.5 a max sclk on or off (20 na typ) full shutdown mode 0.5 a max sclk on or off (20 na typ) power dissipation 4 normal mode (operational) f sample = 200 ksps 7.5 mw max av dd = 5 v, f sclk = 20 mhz 3.6 mw max av dd = 3 v, f sclk = 20 mhz auto shutdown (static) 2.5 w max av dd = 5 v 1.5 w max av dd = 3 v full shutdown mode 2.5 w max av dd = 5 v 1.5 w max av dd = 3 v 1 temperature range : b version: ? 40c to +12 5c. 2 see terminology sectio n. 3 sample tested @ 25 c to ensure compliance. 4 see power vs. throughput rate section.
data sheet ad7923 rev. d | page 5 o f 24 timing specification s av d d = 2.7 v to 5.25 v, v drive av dd , ref in = 2.5 v, t a = t min to t max , unless otherwise noted. 1 table 2 . limit at t min , t max parameter av dd = 3 v av dd = 5 v unit description f sclk 2 10 10 khz min 20 20 mhz max t convert 16 t sclk 16 t sclk t quiet 50 50 ns min minimum quiet time required between cs rising edge and start of next conversion t 2 10 10 ns min cs to sclk set - up time t 3 3 35 30 ns max delay from cs until do ut three - state disabled t 4 3 40 40 ns max data access time after sclk falling edge t 5 0.4 t sclk 0.4 t sclk ns min sclk low pulse width t 6 0.4 t sclk 0.4 t sclk ns min sclk high pulse width t 7 10 10 n s min sclk to dout valid hold time t 8 4 15/45 15/35 ns min/max sclk falling edge to dout high impedance t 9 10 10 ns min din set - up time prior to sclk falling edge t 10 5 5 ns min din hold time after sclk falling edge t 11 20 20 ns min sixteenth sclk falling edge to cs high t 12 1 1 s max power - up time from full power - down / auto shutdown mode 1 sample tested at 25 c to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of av dd ) and timed from a voltage level of 1.6 v. see figure 2 . the 3 v operating range spans from 2.7 v to 3.6 v. the 5 v operating range spans from 4.75 v to 5.25 v. 2 the mark/space ratio for the sclk input is 40/60 to 60/40. 3 measured with the load circuit of figure 2 and defined as the time required for the output to cross 0.4 v or 0.7 v drive . 4 t 8 is derived from the measured time taken by the data outputs to change 0.5 v when loaded with the circuit of figure 2 . the measured numbe r is then extrapolated back to remove the effects of charging or discharging the 50 pf capacitor. this means that the time, quoted in the timing cha racteristics t 8 , is the true bus relinquish time of the part and is independent of the bus loading. 200 a i ol 200 a i oh 1.6v to output pin c l 50pf 03086-002 figure 2 . load circuit for digital output timing specifica tion
ad7923 data sheet rev. d | page 6 of 24 absolute maximum rat ings t a = 25 c , unless otherwise noted. table 3 . parameter rating av dd to agnd ? 0.3 v to +7 v v drive to agnd ? 0.3 v to av dd + 0.3 v analog input voltage to agnd ? 0.3 v to av dd + 0.3 v digital input voltage to agnd ? 0.3 v to +7 v d igital output voltage to agnd ? 0.3 v to av dd + 0.3 v ref in to agnd ? 0.3 v to av dd + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range commercial (b version) ? 40 c to + 125 c storage temperature range ? 65 c to +150 c j unction temperature 150 c tssop package, power dissipation 450 mw ja thermal impedance 150.4 c/w (tssop) jc thermal impedance 27.6 c/w (tssop) lead temperature, soldering vapor phase (60 sec) 215 c infrared (15 sec) 220 c pb - free temperature, sol dering reflow 260(+0)c esd 1.5 kv 1 transient currents of up to 100 ma do not cause scr latchup. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those i ndicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostati c discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
data sheet ad7923 rev. d | page 7 o f 24 pin configuration and function descrip tion 1 2 3 4 5 6 7 8 16 1 5 1 4 1 3 1 2 1 1 1 0 9 din cs agnd ref in av dd av dd sclk v drive dout agnd v in 2 agnd v in 3 v in 1 v in 0 agnd ad7923 top view (not to scale) 03086-003 figure 3. pin configuration table 4 . p in f unction d escriptions pin no. mnemonic function 1 sclk serial clock. logic input. sclk provides the serial clock for accessing data for the part. this clock input is also used as the clock source for the ad7923 conversion process. 2 din d ata in. logic input. data to be written to the control register is provided on this input and is clocked into the register on the falling edge of sclk (see the control register descriptions section). 3 cs chip select. active low logic input. this input provides the dual function of initiating conversions on the ad7923 and framing the serial data transfer. 4, 8, 13, 16 agnd analog ground. ground reference point for all analog circuitry on the ad7923. all analog input signals and any external reference signal should be referred to this agnd voltage. all agnd pins should be connected together. 5, 6 av dd analog power supply input. the av dd range for the ad7923 is from 2.7 v to 5.25 v. for the 0 v to 2 r ef in range, av dd should be from 4.75 v to 5.25 v. 7 ref in reference input for the ad7923. an external reference must be applied to this input. the voltage range for the external reference is 2.5 v 1% for specified performance. 12 to 9 v in 0 to v in 3 analog input 0 through analog input 3. four single - ended analog input channels that are multiplexed into the on - chip track - and - hold. the analog input channel to be converted is selected by using the address bits add1 and add0 of the control register . the a ddress bits in conjunction with the seq1 and seq0 bits allow the sequencer to be programmed. the input range for all input channels can extend from 0 v to ref in or from 0 v to 2 ref in as selected via the range bit in the control register . any unused inpu t channels must be connected to agnd to avoid noise pickup. 14 dout data out. logic output. the conversion result from the ad7923 is provided on this output pin as a serial data stream . the ad7923 serial data stream consists of two leading 0 s, and two a ddress bits indicating which channel the conversion result corresponds to, followed by 12 bits of conversion data, msb first. the output coding can be selected as straight binary or twos complement via the coding bit in the control register . the data bi ts are clocked out of the ad 7923 on the sclk falling edge. 15 v drive logic power supply input. the voltage supplied at this pin determines at which voltage the serial interface operate s .
ad7923 data sheet rev. d | page 8 of 24 typical performance characteristics frequency (khz) snr (db) ? 10 ? 50 ? 30 ? 70 ? 90 ? 110 0 10 20 30 40 60 70 80 90 50 100 03096-004 4096 point fft av dd = 4.75v f sample = 200ksps f in = 50 khz sinad = 70.714db thd = ? 82.853db sfdr = ? 84.815db figure 4 . dynamic performance at 200 ksps input frequency (khz) sinad (db) 75 70 65 60 0 100 03086-005 f sample = 200ksps t a = 25 c range = 0v to ref in av dd = v drive = 5.25v av dd = v drive = 4.75v av dd = v drive = 3.6v av dd = v drive = 2.7v figure 5 . sinad vs. analog input frequency for various supply voltages at 200 ksps supply ripple frequency (khz) psrr (db) 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 20 40 60 80 100 120 140 160 180 200 03086-006 av dd = 5v 200mv p-p sine wave on av dd ref in = 2.5v, 1f capacitor t a = 25c figure 6 . psrr vs. supply ripple frequency input frequency (khz) thd (db) ? 50 ? 90 ? 85 ? 80 ? 75 ? 70 ? 65 ? 60 ? 55 10 100 03086-007 f sample = 200ksps t a = 25 c range = 0v to ref in av dd = v drive = 5.25v av dd = v drive = 4.75v av dd = v drive = 2.7v av dd = v drive = 3.6v figure 7 . thd vs. analog input frequency for various supply voltages at 200 ksps input frequency (khz) thd (db) ? 55 ? 95 ? 90 ? 85 ? 80 ? 75 ? 70 ? 65 ? 60 10 100 03086-008 f sample = 200ksps t a = 25 c av dd = 5.25v range = 0v to ref in r in = 100 ? r in = 1000 ? r in = 10 ? r in = 50 ? figure 8 . thd vs. analog input frequency for various source impedances code inl error (lsb) 1.0 0.6 0.8 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 03096-009 av dd = v drive = 5v temp = 25 c figure 9 . typical inl
data sheet ad7923 rev. d | page 9 o f 24 code dnl error (lsb) 1.0 0.6 0.8 0.4 0.2 0 ? 0.2 ? 0.4 ? 0.6 ? 0.8 ? 1.0 0 512 1024 1536 2048 2560 3072 3584 4096 03096-010 av dd = v drive = 5v temp = 25 c figure 10 . typical dnl
ad7923 data sheet rev. d | page 10 of 24 terminology integral nonlinearity this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1 lsb below the first code transition, and full scale, a point 1 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal, that is, agnd + 1 lsb. offset error match this is the difference in offset error between any two channels. gain error this is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, ref in C 1 lsb) after the offset error has been adjusted. gain error match this is the difference in gain error between any two channels. zero - code error this applies when using the twos complement out put coding option, in particular, with the 2 ref in input range when ?ref in to +ref in is biased around the ref in point. it defined as the deviation of the midscale transition (all 0s to all 1s) from the ideal v in voltage, that is, ref in C 1 lsb. zero - code error match this is the difference in zero - code error between any two channels. positive gain error this applies when using the twos complement output coding option, in particular, with the 2 ref in input range when ?ref in to +ref in is biased around the ref in point. it is the deviation of the last code transition (011 ... 110) to (011 ... 111) from the ideal (that is, +ref in C 1 lsb) after the zero - code error has been adjusted. positive gain error match this is the difference in positive gain error betw een any two channels. negative gain error this applies when using the twos complement output coding option, in particular, with the 2 ref in input range when ?ref in to +ref in is biased around the ref in point. it is the deviation of the first code transition (100 ... 000) to (100 ... 001) from the ideal (that is, ?ref in + 1 lsb) after the zero - code error has been adjusted. negative gain error match this is the difference in negative gain error between any two channels. channel -to - channel isolation channel - to - channel isolation is a measure of the level of cross - talk between channels. it is measured by applying a full - scale 400 khz sine wave signal to all three no nselected input channels and determining how much that signal is attenuated in the selected channel with a 50 khz signal. the figure is given in the worst - case across all four channels for the ad7923. power supply rejection (psr) variations in power supply affect the full - scale transition, but not the converters linearity. power supply rejection is the maxi - mum change in the full - scale transition point from a change in power supply voltage from the nominal value. fi gure 6 shows the power supply rejection ratio v s. supply ripple frequency for the ad7923 with no decoupling. the power sup - ply rejection ratio is defined as the ratio of the power in the adc output at full - scale frequency , f, to the power of a 200 mv p - p sine wave applied to the adc av dd supply of frequency f s : pssr ( db ) = 10 log ( pf / pf s ) pf is equal to the power at frequency f in the adc output; pf s is equal to the power at frequency f s coupled onto the adc av dd supply. track - and - hold acquisition time the track - and - hold amplifier returns into track mode at the end of conversion. track - and - hold acquisition time is the time required for the output of the track - and - hold amplifier to reach its final value, within 1 lsb, after the end of conversion.
data sheet ad7923 rev. d | page 11 o f 24 sign al -to - (nois e + distortion) (sinad ) ratio this is the measured ratio of sinad at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitiza tion process, the more levels, the smaller the quantization noise. the theoretical sinad ratio for an ideal n - bit converter with a sine wave input is given by s inad = (6.02 n + 1.76) db thus for a 12 - bit converter, this is 74 db. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. for the ad7923, it is defined as 1 2 6 2 5 2 4 2 3 2 2 log 20 ) ( v v v v v v db thd + + + + = where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics.
ad7923 data sheet rev. d | page 12 of 24 control register descriptions the control register on the ad7923 is a 12 - bit, write - only register. data is loaded from the din pin of the ad7923 on the falling edge of sclk. the data is transferred on the din line at the same time that the conversion result is read from the part. the data transferred on the din line corresponds to the ad7923 configuration for the next conversion. this requires 16 serial clocks for every data transfer. only the information provided on the first 12 falling clock edges (after cs falling edge) is loaded to the control register . msb denotes the first bit in the data stream. the bit functions are outlined in table 5 . table 5 . control register bit functions msb lsb write seq1 dontc dontc add1 add0 pm1 pm0 seq0 dontc range coding table 6 . bit name description 11 write the value written to this bit of the control register determines whether the following 11 bits are loaded to the control register . if this bit is a 1, the following 11 bits are written to the control register. i f it is a 0, the remaining 11 bits are not loaded to the control register and it remains unchanged. 10 seq1 the seq1 bit in the control register is used with the seq0 bit to control the use of the sequencer function (s ee table 9 ). 7 C 6 add1 add0 these two address bits are loa ded at the end of the present conversion and select w hich analog input channel is converted in the next serial transfer, or they can also be used to select the final channel in a consecutive sequence , as described in table 9 . the selected input channel is decoded , as shown in table 7 . the next channel to be converted on is selected by the mux on the 14th sclk falling edge. channel address bits corresponding to the conversion result are also output on the dout serial data stream prior to the 12 bits of data (s ee the serial interface section ) . 5, 4 pm1 pm0 power management bits . these two bits decode the mode of operation of the ad7923 , as shown in table 8 . 3 seq0 the seq0 bit in the control register is used with the seq1 bit to control the use of the sequencer function. ( s ee table 9 ) . 2 , 9 C 8 dontc dont care. 1 range this b it selects the analog input range to be used on the ad7923. if it is set to 0, the analog input range extend s from 0 v to 2 ref in . if it is set to 1, the analog input range extend s from 0 v to ref in (for the next conversion). for the 0 v to 2 ref in ran ge, av dd = 4.75 v to 5.25 v. 0 coding this bit selects the type of output coding the ad7923 use s for the conversion result. if this bit is set to 0, the output coding for the part is twos complement. if this bit is set to 1, the output coding from the part is straight binary (for the next conversion). table 7 . channel selection add1 add0 analog input channel 0 0 v in 0 0 1 v in 1 1 0 v in 2 1 1 v in 3
data sheet ad7923 rev. d | page 13 o f 24 table 8 . power mode selection pm1 pm 0 mode 1 1 normal operation . in this mode, the ad7923 remains in full power mode, regardless of the status of any of the logic inputs. this mode allows the fastest possible throughput rate from the ad7923. 1 0 full shutdown . in this mode, the ad79 23 is in full shutdown mode with all circuitry on the ad7923 powering down. the ad7923 retains the information in the control register while in full shutdown. the part remains in full shutdown until these bits are changed. 0 1 auto shutdown . in this mo de, the ad7923 automatically enters full shutdown mode at the end of each conversion when the control register is updated. wake - up time from full shutdown is 1 s, and the user should ensure that 1 s has elapsed before attempting to perform a valid conver sion on the part in this mode. 0 0 invalid selection . this configuration is not allowed. sequencer operation the configuration of the seq1 and seq0 bits in the control register allows the user to select a particular mode of operation of the sequencer function. table 9 outlines the three modes of operation of the sequencer. table 9 . sequence selection seq1 seq0 sequence type 0 x this configuration means that the sequence function is not used. the analog input channel selected for each individual conversion is determined by the contents of channel address bits add1 and add0 in each prior write operation. this mode of operation reflects the traditional o peration of a multichannel adc without the sequ encer function being used, where each write to the ad7923 selects the next channel for conversion ( s ee figure 11). 1 0 if the seq1 and seq0 bits are set in this way, the sequence function is no t interrupted upon completion of th e write operation. this allows other bits in the control register to be altered between conversions while in a sequence without terminating the cycle. 1 1 this configurati on is used in conjunction with channel address bits add1 and add0 to program cont inuous conversions on a consecutive sequence of channels from channel 0 to a selected final channel as determined by the channel address bits in the control register (s ee figure 12). figur e 11 reflects the traditional operation of a multichannel adc, where each serial transfer selects the next channel for conversion. in this mode of operation the sequencer function is not used. figure 12 shows how to program the ad 7923 to continuously convert on a sequence of consecutive channels from channel 0 to a selected final channel. to exit this mode of operation and revert back to the traditional mode of operation of a multi - channel adc (as outlined in figure 11 ), ensure that the write bit = 1 and seq1 = seq0 = 0 on the next serial transfer. power-on dummy conversion write bit = 1, seq1 = 0, seq0 = x c s c s 03086-011 din: write to control register, write bit = 1, select coding, range, and power mode. select channel a1, a0 for conversion. seq1 = 0, seq0 = x din: write to control register, write bit = 1, select coding, range, and power mode. select channel a1, a0 for conversion. seq1 = 0, seq0 = x dout: conversion result from previously selected channel a1, a0 figure 11 . seq1 bit = 0, seq0 bit = x flowchart power-on dummy conversion c s c s c s 03086-012 write bit = 1, seq1 = 1, seq0 = 0 write bit = 0 din: write to control register, write bit = 1, select coding, range, and power mode. select channel a1, a0 for conversion. seq1 = 1, seq0 = 1 continuously converts on the selected sequence of channels from channel 0 up to and including the previously selected a1, a0 in the control regisger continuously converts on the selected sequence of channels but will allow range, coding, etc., to change in the con- trol register without interrupting the sequency, provided seq =1, seq0 = 0 dout: conversion result from channel 0 figure 12 . seq1 bit = 1, seq0 bit = 1 flowchart
ad7923 data sheet rev. d | page 14 of 24 theory of operation circuit information the ad7923 is a high speed, 4 - channel, 12 - bit single - supply adc . the part can be operated from a 2.7 v to 5.25 v supply. when operated from either a 5 v or 3 v supply, the ad7923 is capable of throughput rates of 200 ksps. t he conversion time can be a s short as 800 ns when provided with a 20 mhz clock. the ad7923 provides the user with an on - chip track - and - hold a dc and with a serial interface housed in a 16 - lead tssop package. the ad7923 has four , single - ended input channels with a channel sequence r, allowing the user to select a channel sequence through which the adc can cycle with each conse - utive cs falling edge. the serial clock input accesses data from the part, controls the transfer of data written to the adc, and provides the clock source for the successive approximation a dc. the analog input range is 0 v to ref in or 0 v to 2 ref in , depending on the status of the range b it in the control register . for the 0 to 2 ref in range, the part must be op erated from a 4.75 v to 5.25 v av dd supply. the ad7923 provides flexi ble power management options to allow the user to achieve the best power performance for a given throughput rate. these options are selected by program - ming the power management bits, pm1 and pm0, in the control register . converter operation the ad7923 is a 12 - bit successive approximation adc based around a capacitive dac. it can convert analog input signals in the range 0 v to ref in or 0 v to 2 ref in . figure 13 and figure 14 show simplified schematics of the adc. the adc is comprised of a control logic, sar, and capacitive dac, which are used to add and subtract fixed amounts of charge from the sampling c apacitor to bring the comparator back into a balanced condition. figure 13 shows the adc during its acquisition phase. sw2 is closed and sw1 is in position a. the comparator is held in a balanced condition and the s ampling capacitor acquires the signal on the selected v in channel. v in 0 v in 3 agnd a b sw1 sw2 comparator control logic capacitive dac 4k? 03086-013 figure 13 . adc acquisition phase when the adc starts a conversion (see figure 14 ), sw2 open s and sw1 move s to position b, causing the com parator to become unbalanced. the control logic and the capacitive dac are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into balance . when the comparator is rebalanced, the conversion is complete . the control logic generates the adc output code. figure 16 and figure 17 show the adc transfer functions. v in 0 v in 3 agnd a b sw1 sw2 comparator control logic capacitive dac 4k? 03086-014 figure 14 . adc conversion phase analog input fi gure 15 shows an equivalent circuit of the analog input structure of the ad7923. the two diodes d1 and d2 provide esd protection for the analog inputs. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 2 00 mv ; otherwise the se diodes become forward - biased and start conducting current into the substrate. 10 ma is the maximum current these diodes can conduct without causing irreversible damage to the part. capacitor c1 , shown in figur e 15, is typically a round 4 pf and can primarily be attributed to pin capacitance. the resistor r1 is a lumped component made up of the on resistance of the track - and - hold switch and includes the on resistance of the input multiplexer. the total resistanc e is typically about 400 ? . capacitor c2 is the adc sampling capacitor and has a capacitance of 30 pf typi - cally. for ac applications, removing high frequency components from the analog input signal is recommended by using an rc low - pass filter on the rele vant analog input pin. in applications where harmonic distortion and the signal - to - noise ratio are critical, the analog input should be driven from a low impe - dance source. large source impedances significantly affect the ac performance of the adc. this ma y necessitate the use of an input buffer amplifier. the choice of the op amp is a function of the particular application. when no amplifier is used to drive the analog input, the source impedance should be limited to low values. the maximum source impedanc e depend s on the amount of thd that can be tolerated. the thd increase s as the source impedance increas es and performance degrade s ( s ee figure 8 ) . v in c1 4pf c2 30pf r1 d1 d2 av dd conversion phase: switch open tra ck phase: switch closed 03086-015 figure 15 . equivalent analog input circuit
data sheet ad7923 rev. d | page 15 o f 24 adc transfer f unction the output coding of the ad7923 is either straight binary or twos complement, depending on the status of the lsb in the control register . the designed code transitions occur at succes - sive lsb values ( for example , 1 lsb, 2 lsbs). the lsb size is re f in /4096 for the ad7923. the ideal transfer characteristic for the ad7923 when straight binary coding is selected is shown in figure 16 and the ideal transfer characteristic for the ad7923 when twos complement coding is selected i s shown in figure 17. +v r e f ? 1lsb 000...000 0v analog input 111...111 000...001 000...010 111...110 ? ? 111...000 ? 011... 111 ? ? 1lsb 1lsb = v ref /4096 n o t es 1 . v r e f i s ei t h er r ef i n o r 2 r ef i n adc code 03086-016 figure 16 . straight binary transfer characteristic ? v r e f + 1lsb adc code analog input +v r e f ? 1lsb 1lsb = 2 v ref / 4 096 v r e f ? 1lsb 100...000 011...111 100...001 100...010 011...110 ? ? 000...001 111...111 ? ? 000...000 03086-017 figure 17 . twos complement transfer characteristic with ref in ref in input range handling bipolar inpu t signals figure 18 shows how useful the combination of the 2 ref in input range and the twos complement output coding scheme is for handling bipolar input signals. if the bipolar input signal is biased ar ou nd ref in and twos compl ement output coding is selected, then ref in becomes the zero - code point, ?ref in is negative full scale, and + ref in becomes positive full scale with a dynamic range of 2 ref in . r3 r2 r4 ref in v in 0 v in 3 ad7923 dsp/ p v dd 0.1 f v a v dd v drive dout twos complement + ref in ref in ? ref in 011...111 000...000 100...000 (= 0v) (= 2 ref in ) 0v v r1 r1 = r2 = r3 = r4 v dd v ref ? ? 03086-018 figure 18 . handling bipolar signals
ad7923 data sheet rev. d | page 16 of 24 typical connection d iagram figure 19 shows a typical con nection diagram for the ad7923. in this setup the agnd pin is connected to the analog ground plane of the system. in figure 19 , ref in is connected to a decoupled 2.5 v supply from a reference source, the ad780, to provide an analog input range of 0 v to 2.5 v (if the range bit is 1) or 0 v to 5 v (if the range bit is 0). although the ad7923 is connected to a v dd of 5 v, the serial interface is connected to a 3 v microprocessor. the v drive pin of the ad7923 is connected to the same 3 v supply of the microprocessor to allow a 3 v logic interface (see the digital inputs section). the conversion result is output in a 16 - bit word. this 16 - bit data stream consists of two leading 0 s, two address bits indicating whic h channel the conversion result corresponds to, followed by the 12 bits of conversion data. for applications where power consumption is a concern, the power - down modes should be used between conversions or bursts of several conversions to improve power per formance. see the modes of operation section. serial interface ad780 2.5v ad7923 0.1 f c/ p 0.1 f 10 f 3v supply 5v supply 0.1 f 10 f a gnd a v dd ? ? 0 v t o ref in sclk dout c s din v drive ref in notes 1. all unused input channels must be connected to agnd. v in 0 v in 3 03086-019 figure 19 . typical connection diagram analog input selection any one of four analog input channels can be selected for conversion by programming the multipl ex er with address bits add1 and add0 in the control register . the channel configurations are shown in table 7 . the ad7923 can also be configured to automatically cycle through selected channels. the sequencer feature is accessed via the seq1 and seq0 bits in the control register (s ee table 9 ). the ad7923 can be programmed to continuously convert on a number of consecutive channels in ascending order from channel 0 to a selected final channel as determined by channel address bits add1 and add0. this is possible if the seq1 and seq0 bits are set to 1, 1. the next serial transfer then act s on the sequence programmed by executing a conversion on channel 0. the next serial transfer result s in a conversion on channe l 1, and so on, until the channel selected via address bits add1 and add0 is reached. it is not necessary to write to the control register again once a sequencer operation has been initiated. the write bit must be set to 0 or the din line must be set low t o ensure that the control register is not accident ally overwritten or the sequence operation is interrupted. if the control register is written to at any time during the sequence, the user must ensure that the seq1 and seq0 bits are set to 1, 0 to avoid in terrupting the automatic co nversion sequence. this pattern continue s until the ad7923 is written to and the seq1 and seq0 bits are configured with any bit combination except 1, 0 , resulting in the termination of the sequence. if uninter - rupted, however ( wr ite bit = 0, or write bit = 1 and seq1 and seq0 bits are set to 1, 0), then upon completion of the sequence, the ad7923 sequencer return s to channel 0 and commence s the sequence again. regardless of which channel selection method is used, the 16- bit word output from the ad7923 during each conversion always contain s two leading 0 s, and two channel address bits that the conversion result corresponds to, followed by the 12 - bit conversion result. (s ee the serial interface section ) . dig ital inputs the digital inputs applied to the ad7923 are not limited by the maximum ratings that limit the analog inputs. instead, the digital inputs applied can go to 7 v and are not restricted by the av dd + 0.3 v limit as on the analog inputs. another ad vantage of sclk, din, and cs not being restricted by the av dd + 0.3 v limit is that possible power supply sequencing issues are avoided. if cs , din, or sclk are applied before av dd , there is no risk of latchup as there would be on the analog inputs if a signal greater than 0.3 v were applied prior to av dd . v drive the ad7923 also has the v drive feature. v drive controls the voltage at which the serial interface operates. v drive allows the adc to easily interface to both 3 v and 5 v processors. for example, if the ad7923 were operated with an av dd o f 5 v, t h e v drive pin could be powered from a 3 v supply. the ad7923 has a larger dynamic range with an av dd of 5 v while still being able to interface to 3 v processors . care should be taken to ensure that v drive does not exceed av dd by more than 0.3 v (s ee the absolute maximum ratings section ) . reference an external reference source should be used to supply the 2.5 v reference to the ad7923. er rors in the reference source result in gain errors in t he ad7923 transfer function and add to the specified full - scale errors of the part. a capacitor of at least 0.1 f should be placed on the ref in pin. suitable reference sources for the ad7923 include the ad780, ref 19 2 , and the ad1582.
data sheet ad7923 rev. d | page 17 o f 24 if 2.5 v is applied to the ref in pin, the analog input range can be either 0 v to 2.5 v or 0 v to 5 v, depending on the setting of the range bit in the control register . modes o f operation the ad7923 has a number of diff erent modes of operation, which are designed to provide flexible power management options. these options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. the mode of operation of the ad7923 is co ntrolled by the power management bits, pm1 and pm0, in the control register , as detailed in table 8 . when power supplies are first applied to the ad7923, care should be taken to ensure that the part is placed in the required mode of operation (s ee the powering up the ad7923 section ) . normal mode (pm1 = pm0 = 1) this mode is intended for the fastest throughput rate perfor - mance where the user does not have to worry about power - up time since the ad7923 remain s fully powered at all time s. figure 20 shows the general diagram of the operation of the ad7923 in this mode. the conversion is initiated on the falling edge of cs and the track - and - hold enter s hold mode , as described in the serial interface section. the data presented to the ad7923 on the din line during the first 12 clock cycles of the data transfer is loaded into the control register (provided the write bit is set to 1). the part r emain s fully powered up in normal mode at the end of the conversion as long as pm1 and pm0 are set to 1 in the write transfer during that same conversion. to ensure continued operation in normal mode , pm1 and pm0 must both be loaded with 1 on every data tr ansfer, assuming a write operation is taking place. if the write bit is set to 0, the power management bits are left unchanged and the part remain s in normal mode . sixteen serial clock cycles are required to complete the conver - sion and access the conversi o n result. the track - and - hold go back into track on the 14th sclk falling edge. cs may then idle high until the next conversion or may idle low until sometime prior to the next conversion (effectively idling cs low). for specified performance, the throughput rate should not exceed 200 ksps, which means there should be no less than 5 s between consecutive falling edges of cs when converting. the act ual frequency of the sclk used determine s the duration of the conversion within this 5 s cycle; however, once a conver - sion is complete, and cs has returned high, a minimum of the quiet time, t quiet , must elapse before bringing cs low again to initia te another conversion. 1 12 c s sclk dout din 16 2 leading zeros + 2 channel identifier bits + conversion result data into control register control register data is loaded on the first 12 sclk cycles. 03086-020 figure 20 . normal mode operation full shutdown (pm1 = 1, pm0 = 0) in this mode, all internal circuitry on the ad7923 is powered down. the part retains information in the control register during full shutdow n. the ad7923 remains in full shutdown until the power management bits in the control register , pm1 and pm0, are changed. if a write to the control register occurs while the part is in full shutdown , with the power management bits changed to pm0 = pm1 = 1, normal mode , the part begin s to power up on the cs rising edge. the track - and - hold that was in hold while the part was in full shutdown return s to track ing on the 14th sclk falling edge. a full 16 - sclk transfer must occur to ensure that the control register contents are updated; however, the dout line is not driven during this wake - up transfer. to ensure that the part is fully powered up, t power up (t 12 ) should have elapsed before the next cs falling edge; othe rwise invalid data is read if a conversion is initiated before this time. figure 21 shows the general diagram for this sequence. auto shutdown (pm1 = 0, pm0 = 1) in this mode, the ad7923 automatically enters shutdown at the end of each conversion when the control register is updated. when the part is in shutdown, the track - and - hold is in hold mode . figure 22 shows the general diagram of the operation of the ad7923 in this mode. in shutdown mode all internal circuitry on the ad7923 is powered down. the part retains information in the control register during shutdown. the ad7923 remains in shutdown until the next cs falling edge it receives. on this cs falling edge , the track - and - hold that was in hold while the part was in shutdown return s to track ing . wa ke - up time from auto shutdown is 1 s maximum, and the user should ensure that 1 s has elapsed before attempting a valid conversion. when running the ad7923 with a 20 mhz clock, one dummy 16 sclk transfer should be sufficient to ensure that the part is fully powered up. during this dummy transfer, the contents of the control register should remain unchanged, therefore the write bit should be 0 on the din line. depen ding on the sclk frequency used, this dummy transfer may affect the achievable throughput rate of the part, with every other data transfer being a valid conversion result. if, for example, the maximum sclk frequency of 20 mhz is used, the auto shut - down mo de could be used at the full through - out rate of 200 ksps without affecting the throughput rate at all.
ad7923 data sheet rev. d | page 18 of 24 only a portion of the cycle time is taken up by the conversion time and the dummy transfer for wake up. in this mode, the power con - sumption of the part is greatly reduced because the part enter s shutdown at the end of each conversion. when the control register is programmed to move into auto shutdown , it does so at the end of the conversion. the user can move the adc in and out of the low power state by c ontrolling the cs signal. powering up the ad7923 when supplies are first applied to the ad7923, the adc can power up in any of the operating modes of the part. to ensure that the part is placed into the required operating mode, the u ser should perform a dummy cycle operation , as outlined in figure 23 through figure 25. the dummy conversion operation must be performed to place the part into the desired mode of operation. to ensure that the part is in normal mode , this dummy cycle operation can be performed with the din line tied high, that is , pm1, pm0 = 1, 1 (depending on other required settings in the control register), but the minimum power - up time of 1 s must be allowed from the ris ing edge of cs , where the control register is updated, before attempting the first valid conversion. this is to allow for the possibility that the part initially powered up in shutdown. if the desired mode of operation is full shutdo wn , then again only one dummy cycle is required after supplies are applied. in this dummy cycle, the user simply sets the power management bits, pm1, pm0 = 1, 0, and upon the rising edge of cs at the end of that serial transfer, the par t enter s full shutdown . if the desired mode of operation is auto shutdown after supplies are applied, two dummy cycles are required, the first with din tied high and the second dummy cycle to set the power manage - ment bits pm1 and pm0 = 0,1. on the sec ond cs rising edge after the supplies are applied, the control register contain s the correct information and the part enter s auto shutdown mode as programmed. if power consumption is of critical concern, then in the first dummy cycle the user may set pm1, pm0 = 1, 0, that is , full shutdown , and then place the part into auto shutdown in the second dummy cycle. for illustration purposes, figure 25 is shown with din tied high on the first dummy cycle in this case . figure 23, figure 24 , and figure 25 each show the required dummy cycle(s) after supplies are applied in the case of normal mode , full shutdown mode , and auto shutdown mode , respec t - ively, being the desired mode of operation. c s sclk dout din 1 14 1 6 1 14 16 part is in full shutdown part begins to power up on cs rising edge as pm1 = pm0 =1 the part is fully powered up once t power up has elapsed contr ol register is lo aded on the first 12 clocks. pm1 = 1, pm0 = 1 to keep the p ar t in normal mode, lo ad pm1 = pm0 = 1 in contr ol register channel identifier bits + conversion result data into control register data into control register t 12 03086-021 figure 21 . full shutdown mode operation 1 c s sclk dout din 16 1 16 1 16 dummy conversion channel identifier bits + conversion result invalid data channel identifier bits + conversion result control register is loaded on the first 12 clocks, pm1 = 0, pm0 = 1 control register contents should not change, write bit = 0 to keep part in this mode, load pm1 = 0, pm0 = 1 in control register or set write bit = 0 part is fully powered up part begins to power up on cs falling edge part enters shutdown on cs rising edge as pm1 = 0, pm0 =1 12 12 12 part enters shutdown on cs rising edge as pm1 = 0, pm0 =1 data into control register data into control register data into control register 03086-022 figure 22 . auto shutdown mode operation
data sheet ad7923 rev. d | page 19 o f 24 invalid data channel identifier bits + conversion result din line high for first dummy conversion data into control register to keep the part in normal mode, load pm1 = pm0 = 1 in control register 1 14 1 6 1 14 16 allow t power to elapse if in shutdown at power-on part begins to power up on cs rising edge as pm1 = pm0 = 1 part is in unknown mode after power-on c s sclk dout din 03086-023 t 12 figure 23 . placing the ad7923 into normal mode after supplies are first applied invalid data 1 14 16 pa r t en t er s sh u t d o w n o n c s r i si n g ed g e a s pm1 = pm0 = 0 part is in unknown mode after power-on c s sclk dout din data into control register control register is loaded on the first 12 clocks. pm1 = 1, pm0 = 0 03086-024 figure 24 . placing the ad7923 into full shutdown mode after supplies are first applied invalid data invalid data din line high for first dummy conversion data into control register control register is loaded on the first 12 clocks. pm1 = 0, pm0 = 1 1 14 1 6 1 14 16 part is in unknown mode after power-on c s sclk dout din 03086-025 pa r t en t er s a u t o sh u t d o w n o n c s r i si n g ed g e a s pm1 = 0 , pm0 = 1 figure 25 . placing the ad7923 into auto shutdown mode after supplies are first ap plied power vs . throughput rate in auto shutdown mode , the average power consumption of the adc can be reduced at any given throughput rate. the power saving depend s on the sclk frequency used, that is , conversion time. in some cases where the conversion time is a large propor - tion of the cycle time, the throughput rate need s to be reduced to take advantage of the power - down modes. assuming a 20 mhz sclk is used, the conversion time is 800 ns, but the cycle time is 5 s when the sampling rate is at a maxi mum of 200 ksps. if the ad7923 is placed into shutdown for the remainder of the cycle time, then on average far less power is consumed in every cycle compared to leaving the device in normal mode . furthermore, figure 26 shows how, as the throughput rate is reduced, the part remains in its shutdown longer and the average power consumption drops accordingly over time.
ad7923 data sheet rev. d | page 20 of 24 for example, if the ad7923 is operated in a continuous samp - ling mode, with a throughput rate of 200 ksps and an sclk of 20 mhz (av dd = 5 v), and the device is placed in auto shut - down mode , that is , if pm1 = 0 and pm0 = 1, then the power consumption is calculated as follows: the maximum power dissipation during conversion is 13.5 mw (i dd = 2.7 ma max, av dd = 5 v). if th e power - up time from auto shutdown is one dummy cycle, that is 1 s, and the remaining conversion time is another cycle, that is , 800 ns, then the ad7923 can be said to dissipate 13.5 mw for 1.8 s during each conversion cycle. for the remainder of the con version cycle, 3.2 s, the part remains in shutdown . the ad7923 can be said to dissipate 2.5 w for the remaining 3.2 s of the conver - sion cycle. if the throughput rate is 200 ksps, the cycle time is 5 s and the average power dissipated during each cycl e is (1.8/5) (13.5 mw) + (3.2/5) (2.5 w) = 4.8616 mw. figure 26 shows the maximum power v s. throughput rate when using the auto shutdown mode with 5 v and 3 v supplies. throughput (ksps) power (mw) 10 1 0.1 0.01 0 60 40 20 100 80 180 160 140 120 100 03086-026 av dd = 5v av dd = 3v figure 26 . power vs. throughpu t rate serial interface figure 27 shows the detailed timing diagrams for serial inter - facing to the ad7923. the serial clock provides the conversion clock and controls the transfer of information to and from the ad7923 during each conversion. the cs signal initiates the data transfer and conversion process. the falling edge of cs puts th e track - and - hold into hold mode and t akes the bus out of three - state; the analog input is sampled at t his point. the conversion is also initiated at this point and require s 16 sclk cycles to complete. the track - and - hold returns to track mode at point b on the 14th sclk falling edge , as shown in figure 27. on the 16th sclk falling e dge the dout line returns to three - state. if the rising edge of cs occurs before 16 sclks have elapsed, the conversion is terminated, the dout line returns to three - state , and the control register is not updated; otherwise dout retur ns to three - state on the 16th sclk falling edge, as shown in figure 27. sixteen serial clock cycles are required to perform the conver - sion process and to access data from the ad7923. for the ad7923, the 12 bits of data are precede d by two leading 0 s and channel address bits add1 and add0, identifying which channel the result corresponds to. cs going low clocks out the first leading 0 to be read by the microcontroller or dsp on the first falling edge of sclk. the first falling edge of sclk also clock s out the second leading 0 to be read by the microcon - troller or dsp on the second sclk falling edge, and so on. the remaining two address bits and 12 data bits are then clocked out by subsequent sclk falling edges , beginning with the first address bit add1, thus the second falling clock edge on the serial clock has the second leading 0 and also clocks out address bit add1. the final bit in the data transfer is valid on the 16th falling edge, having been clocked out on the previous (15th) falling edge. writing information to the control register takes place on the first 12 falling edges of sclk in a data transfer, assuming the msb, that is , the write bit, has been set to 1. the 16 - bit word read from the ad7923 always contain two leading 0 s, two channel address bits that the conversion result corresponds to, followed by the 12 - bit conversion result. writing between conversions as outlined in the operating modes section, not less than 5 s should be left betwee n consecut ive valid conversions. there is one exception, however : c onsider the case when writing to the ad7923 to power it up from shutdown prior to a valid conver - sion. the user must write to the part to tell it to power up before it can convert successfully. once the serial write to power up has finished, the user m ight want to perform the conversion as soon as possible without waiting an additional 5 s before bringing cs low for the conversion. in this case, as long as there is a minimum of 5 s between each valid conversion, only the quiet time between the cs rising edge at the end of the write to power up and the next cs falling edge needs to be met. figure 28 illustra tes this point. note that when writing to the ad7923 between these valid conversions, the dout line is not driven during the extra write operation. it is critical that an extra write operation as outlined above is never issued between valid conversions whe n the ad7923 is executing a sequence function, because the falling edge of cs in the e xtra write moves the mux to the next channel in the sequence. this means that when the next valid conversion takes place a channel result would be missed.
data sheet ad7923 rev. d | page 21 o f 24 c s sclk dout din t 5 t 11 t 8 t quiet t conver t 1 2 3 4 5 6 1 1 1 2 1 3 1 4 1 5 1 6 three- state zer o add1 add0 db11 db10 db4 db3 db2 db1 db0 three- state 2 identification bits zero b write seq1 dontc dontc add1 add0 coding dontc dontc dontc dontc t 9 t 2 t 3 t 10 t 6 t 7 t 4 03086-027 figure 27 . serial interface timing diagram c s 1 16 1 16 1 16 sclk valid data valid data dout power-up din t cycle 5s min t quiet min 03086-028 figure 28 . general timing diagram microprocessor inter facing the serial interface on the ad7923 allows the part to be directly connected to a rang e of many different microprocessors. this section explains how to interface the ad7923 with some of the more common microcontroller and dsp serial interface protocols. ad7923 - to - tms320c541 the serial interface on the tms320c541 uses a continuous serial clo ck and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the ad7923. the cs input allows easy interfacing between the tms320c541 and the ad7923 without any glue logic required. the serial port of the tms320c541 is set up to operate in burst mode with internal clkx0 (tx serial clock on serial port 0) and fsx0 (tx frame sync from serial port 0). the serial port control register (spc) must have the following setup: fo = 0, fsm = 1, mcm = 1, and txm = 1. the connection diagram is shown in figure 29 . it should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the tms320c541 provides equidistant sampling. the v drive pin of the ad7923 takes the same supply voltage as the tms320c541. this allows the adc to operate at a higher voltage than the serial interface, that is , the tms320c541, if necessary. tms320c541 1 ad7923 1 clkx clkr dr dt fsx fsr v dd sclk dout din c s 1 additional pins removed for clarity. 03086-029 v drive figure 29 . interfacing to the tms3 20c541 ad792 3 - to - adsp - 21xx the adsp - 21xx family of dsps is interfaced directly to the ad7923 without any glue logic required. the v drive pin of the ad7923 takes the same supply voltage as the adsp - 218x , which allows the adc to operate at a higher voltage t han the serial interface, that is , adsp - 218x, if necessary. the sport0 control register should be set up as follows: tfsw = rfsw = 1, alternate framing invrfs = invtfs = 1, active low frame signal dtype = 00, right justify data slen = 1111, 16 - bit data - wor ds isclk = 1, internal serial clock tfsr = rfsr = 1, frame every word irfs = 0 itfs = 1
ad7923 data sheet rev. d | page 22 of 24 the connection diagram is shown in figure 30 . the adsp - 218x has the tfs and rfs of the sport tied together, with tfs set as an output and rfs s et as an input. the dsp operates in alternate framing mode and the sport control register is set up as described. the frame synchronization signal generated on the tfs is tied to cs and, as with all signal processing applica - tions, e quidistant sampling is necessary. however, in this example, the timer interrupt is used to control the sampling rate of the adc, and under certain conditions equidistant sampling m ight not be achieved. v drive ad7923 1 adsp-218x 1 sclk dr rfs tfs dt sclk dout c s din 1 additional pins removed for clarity. v dd 03086-030 figure 30 . interfacing to t he adsp - 218x the timer register , for instance, is loaded with a value that provide s an interrupt at the required sample interval. when an interrupt is received, a value is transmitted with tfs/dt (adc control word). the tfs is used to control the rfs and t herefore the reading of data. the frequency of the serial clock is set in the sclkdiv register . when the instruction to transmit with tfs is given ( that is , ax0 = tx0), the state of the sclk is checked. the dsp wait s until the sclk has gone high, low, and high before the transmission start s . if the timer and sclk values are chosen such that the instruction to transmit occurs on or near the rising edge of sclk, the data can be transmitted, or it can wait until the next clock edge. for example, if the adsp - 21 89 has a 20 mhz crystal such that it has a master clock frequency of 40 mhz, then the master cycle time is 25 ns. if the sclkdiv register is loaded with the value 3, then a sclk of 5 mhz is obtained, and eight master clock periods elapse for every sclk per iod. depending on the throughput rate selected, if the timer registers are loaded with the value 803, 100.5 sclks occur between interrupts and subsequently between transmit instructions. this situation result s in nonequidistant sampling since the transmit instruction occurs on a sclk edge. if the number of sclks between interrupts is a n integer of n, equidistant sampling is implemented by the dsp. ad7923 - to - dsp563xx the connection diagram in figure 31 shows how the ad7923 can be con nected to the synchronous serial interface (essi ) of the dsp563xx family of dsps from motorola. each essi (two on board) is operated in synchronous mode (syn bit in crb = 1) , with an internally generated word length frame sync for both tx and rx (bits fsl1 = 0 and fsl0 = 0 in crb). normal operation of the essi is selected by making mod = 0 in the crb. set the word length to 16 by setting bits wl1 = 1 and wl0 = 0 in cra. the fsp bit in the crb should be set to 1 so the frame sync is negative. it should be no ted that for signal processing applications, it is imperative that the frame synchro - nization signal from the dsp563xx provides equidistant sampling. in the example shown in figure 31 , the serial clock is taken from the essi , there fore the sck0 pin must be set as an output, sckd = 1. the v drive pin of the ad7923 takes the same supply voltage as the dsp563xx , which allows the adc to operate at a higher voltage than the serial interface, that is , dsp563xx, if necessary. ad7923 1 dsp563xx 1 sck srd std sc2 sclk dout c s din v drive 1 additional pins removed for clarity. v dd 03086-031 figure 31 . interfacing to the dsp563xx
data sheet ad7923 rev. d | page 23 o f 24 application hints grounding and layout the ad7923 has very good immunity to noise on the power supplies as can be seen by the psrr v s. supply ripple frequency plot, figure 6 . h owever, care should still be taken in grounding and layout. the printed circuit board that houses the ad7923 should be designed such that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be separated easily. a minimum etch technique is generally best for ground planes since it gives the best shielding. all three agnd pins of the ad7923 should be sunk into the agnd plane. digital and analog ground planes should be joi ned at only one place. if the ad7923 is in a system where multiple devices require an agnd to dgnd connection, the connection should still be made at one point only, a star ground point that should be established as close as possible to the ad7923. avoid r unning digital lines under the device since they couple noise onto the die. the analog ground plane should be allowed to run under the ad7923 to avoid noise coupling. the power supply lines to the ad7923 should use as large a trace as possible to provide l ow impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, like clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never be run near the analog inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduce s the effects of feedthrough through the board. a microstrip technique is by far the best technique , but is not always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground planes , while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decouple d with 10 f tantalum in parallel with 0.1 f capa - citors to agnd. to achieve the best results from these decoupling components, they must be placed as close as pos - sible to the device, ideally right up against the device. the 0.1 f capacitors should have low effective series resistance (esr) and low effective series inductance (esi), such as the common ceramic types or surface mount types, which provide a low impedance path to ground at high frequencies to handle transient currents from internal logic swi tching.
ad7923 data sheet rev. d | page 24 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 32 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters ordering guide model 1 , 2 temperature range linearity error (lsb) 3 package option package description AD7923BRU ? 40 c to + 12 5 c 1 ru - 16 16 - lead tssop AD7923BRUz ?40c to +125c 1 ru -16 16- lead tssop AD7923BRUz - reel ?40c to +125c 1 ru -16 16- lead tssop AD7923BRUz - reel7 ?40c to +125c 1 ru -16 16- lead tssop ad7923wyruz - reel7 ?40c to +125c 1 ru -16 16- lead tssop 1 z = ro hs compliant part. 2 w = qualified for automotive applications. 3 linearity error refers to integral linearity error. automotive products the ad 7923 w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that d iffer from the commercial models; therefore, designers should review the specifications section of this data sheet carefully. only the automotive grade products shown are available for use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. ?200 2 C 201 3 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d 03086 - 0- 6/ 13 ( d )

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